ISE Design Suite: Logic Edition
Front-to-back FPGA Logic Design
The ISE® Design Suite: Logic Edition includes exclusive tools and technologies to help achieve optimal design results. These include PlanAhead™ for advanced FPGA floorplanning, ChipScope™ Pro for in-circuit verification, and SmartGuide for faster incremental implementation.
From product installation through design verification, ISE Design Suite 11 helps you make maximum use of your time and design resources. The ISE Design Suite: Logic Edition provides:
A complete design environment for your RTL-based design needs with exclusive technologies such as:
- ChipScope Pro and the ChipScope Pro Serial I/O Toolkit for extensive on-chip verification
- ISE™ Simulator, a complete, full-featured HDL simulator integrated within the ISE design environment
- PlanAhead, a complete environment for IO pin planning, floorplanning and detailed graphical design analysis
- Multi-processor support allowing distributed processing to speedup implementations
- Goal-based implementation allows automatic assignment of settings to deliver results specific to your design objectives (e.g., Performance, Runtime, Area, or Power)
- Industry first IEEE encryption for Virtex-5 FPGA Hard-IP simulation models provides an average 2X faster simulation runtime compared with SmartModels
ISE Design Suite: Embedded Edition
Integrated Embedded Design Solution
The ISE® Design Suite: Embedded Edition includes all of the features and technologies found in the ISE Design Suite: Logic Edition plus additional tools and IP required for Xilinx Platform FPGAs designs with embedded PowerPC hard processor cores and/or MicroBlaze soft processor cores.
Quickly configure a hardware platform and create a custom software design that includes the appropriate libraries as well as automated generation of device drivers and a complete BSP (Board Support Package). This productive environment saves time by accelerating design steps that would otherwise be manual and error-prone.
Create your own custom-processing platform while reducing your system cost by consolidating external functions into an FPGA. Select the perfect balance of feature and size for your system, and optimize hardware/software design trade-offs for the best price-performance results that meet your exacting requirements.
ISE Design Suite: DSP Edition
For High-Performance DSP systems
The ISE® Design Suite: DSP Edition includes all of the features and technologies found in the ISE Design Suite: Logic Edition plus additional tools and DSP-specific IP addressing the special needs of the DSP designer. Developers with little FPGA design experience can quickly create production quality FPGA implementations of DSP algorithms in a fraction of traditional RTL development times.
The ISE Design Suite: DSP Edition delivers a comprehensive design suite that extend The Mathworks widely popular MATLAB and Simulink® modeling environments for FPGA design. This DSP design environment can be used early in the design flow to explore hardware solutions for high-level algorithms or to assemble complete DSP systems for production that are highly optimized and include RTL, IP and embedded processing.
The ISE Design Suite: DSP Edition includes System Generator for DSP™ providing the industries most flexible, integrated and powerful DSP development environment for FPGAs.
System Generator for DSP, included with the ISE Design Suite: DSP Edition, comes complete with an optimized, bit and cycle accurate library for assembling sophisticated signal processing systems. Xilinx algorithmic IP is an integral part of this library and is used to rapidly create efficient implementations of common DSP building blocks such as FIR filters, FFTs and forward error correction (FEC) blocks.
With its comprehensive environment, the ISE Design Suite: DSP Edition streamlines development using industry standard development tools for your DSP designs. Using MATLAB and Simulink from The Mathworks™, coupled with Xilinx System Generator for DSP, you can now model, simulate, and verify your signal processing algorithms on your target hardware platform without leaving the Simulink environment.
The design flow typically involves the following steps:
- Development and verification of the hardware model using industry-standard tools from The MathWorks in conjunction with Xilinx System Generator for DSP.
- Generation of an HDL circuit representation that is bit- and cycle-true, meaning that the behavior is guaranteed to match the functionality seen in the original model.
- Synthesis of the design and generation of a bitstream that can be used to program the FPGA. The error-prone and time-consuming step of having an FPGA designer translate the system engineer’s design into HDL is thus eliminated.
ISE Design Suite Features
ChipScope Pro and the Serial I/O Toolkit
ChipScope™ Pro tool inserts logic analyzer, bus analyzer, and virtual I/O low-profile software cores directly into your design, allowing you to view any internal signal or node, including embedded hard or soft processors. Signals are captured at or near operating system speed and brought out through the programming interface, freeing up pins for your design. Captured signals can then be analyzed through the included ChipScope Pro Logic Analyzer.
The ChipScope Pro Serial I/O Toolkit provides fast and easy interactive setup and debug of serial I/O channels in high-speed FPGA designs. The ChipScope Pro Serial I/O Toolkit allows you to measure bit-error ratios on multiple channels and adjust high-speed serial transceiver parameters in real-time while you serial I/O channels interact with the rest of the system.
ChipScope Pro Key Features:
- Analyze any internal FPGA signal, including embedded processor busses
- Inserts low-profile, configurable software cores either during design capture, or after synthesis
- All ChipScope Pro cores are available through the Xilinx CORE Generator™ System
- Enhancements to the Virtex-5 System Monitor console make it easier to access on-chip temperature, voltage, and external sensor
- Change probe points without re-synthesizing
- Debug over an internet connection using remote debug, from your office to the lab
ChipScope Pro Serial I/O Toolkit Key Features:
- Fast and easy interactive setup and debug of FPGA serial I/O channels
- Measure bit-error ratios on multiple channels, adjust high-speed serial transceiver parameters in real-time while your serial I/O channels are interacting with the rest of the system
- Built-in pattern generator and pattern receiver with all the standard Serial I/O data packets
- Requires only JTAG programming port access to your board, no extra pins need for dedicated high-speed serial debug or setup
PlanAhead Design Analysis Tool
A faster, more efficient design solution to help achieve your performance goals.
PlanAhead™ streamlines design iterations between synthesis and implementation. With PlanAhead, you can easily view implementation and timing results to analyze critical logic, and make targeted decisions to improve design performance with floorplanning, constraint modification, and multiple implementation tool options. It helps you make tradeoffs between RTL Coding and Synthesis and Implementation, with extensive design exploration and analysis features.
With convenient access through the integration with the ISE Project Navigator, PlanAhead extends the methodology of the logic design flow to help users get the most out of their design through floorplanning, multiple implementation runs, hierarchy exploration, quick timing analysis, and block based implementation.
PlanAhead also provides easy and convenient method of placing the ChipScope Pro debug cores to make simplify the process of on-chip verification.
Simplified Pin Planning
PlanAhead provides features to help users simplify the complexities of pin assignments with an environment for fully automatic or semi-automated assignment of I/O ports to physical Package Pins.
PlanAhead includes an implementation exploration tool. By managing multiple implementation runs, PlanAhead allows the user to execute multiple implementation runs based on strategies they’ve defined or predefined strategies shipped as factory defaults. In a Linux environment, PlanAhead provides the ability to run the implementation on remote hosts.
Block-Based, Incremental Design
PlanAhead supports a hierarchical, block-based, modular and incremental design methodologies, enabling designers to change only part of the design, leaving placement of the rest intact, thereby shortening design iterations. It helps you consistently maintain the required performance, even while making frequent changes.
PlanAhead includes functionality to check limits for Weighted Average SSO (WASSO) analysis. This allows designers to more easily limit the amount of ground bounce present immediately at the output of the FPGA and prevent corruption of the operation of other devices driven by the FPGA.
TimeAhead is a flexible timing analyzer integrated into PlanAhead. It allows you to estimate route delays before running place and route. Using the PlanAhead block-based approach, the accuracy of timing estimates will improve as blocks in the design are implemented through place and route.